1. Field of the Invention
The present invention generally relates to the testing of logic circuits and more particularly to a method and system of determining the physical location of defects by referring to the previously known physical location of latches which contain failing data.
2. Description of Related Art
Identifying the locations of defects on a wafer is one of the main tools used to determine the attributes of defects, such as clustering, wafer scale patterns, spatial trends, etc. To see such trends or patterns, defects on large numbers of wafers are identified and their locations displayed. Traditionally, this is done by physically identifying the defects and plotting their locations on a wafer map. This is a very time consuming process and can be done only occasionally for full wafers. Otherwise, it is done only incidentally for failing chips that have been identified in some sense as xe2x80x9cinterestingxe2x80x9d.
It is, therefore, an object of the present invention to provide a structure and method for identifying a physical location of a defect in a logic circuit based on a physical location of a logic latch having failing data. The logic circuit includes a plurality of logic latches, each having a predetermined physical location within the logic circuit. The contents of the logic latch is determined by a clock signal and by logic devices that are generally in the neighborhood of the latch. Therefore, the latch having incorrect data indicates the presence of a defect in the latch itself or on the clock line or in the logic devices in the vicinity of the latch.
With the invention, a map of the physical location of the logic latch having failing data can be easily made and the proximity of the logic latches having failing data can be determined. The invention can be used to recognize a pattern of the logic latches having failed data to determine if similar patterns of failing locations occur on other similarly manufactured logic circuits. Therefore, the manufacturing process for a logic circuit layout can be adjusted based on the pattern. Also, potential defect locations can be determined by examining visual inspection data in the vicinity of failing logic latches. Thus, the invention uses information about the defect to improve manufacturing yield and/or to improve yield analysis.
In another embodiment, the invention is a method of locating a physical location of a defect in a logic circuit that includes establishing test connections with the logic circuit, identifying physical locations of the logic latches and supplying test signals, wherein defective portions of the logic circuit will produce failing data in the logic latches thereby identifying a physical location of the defect in the logic circuit based on a physical location of a logic latch having failing data.
With the invention somewhat accurate full wafer maps can be obtained within minutes. The resulting wafer maps can help identify defect categories, thereby improving manufacturing yield and/or yield analysis, etc. Because of the rapid turnaround achieved with the invention, the productivity of test and failure analysis is improved, and the yield learning time is shortened.